Pulse Width Insensitive Design and Verification Methods

Pulse Width Insensitive Design and Verification Methods

Blog Article

Many embedded controllers have some critical system states that depend on an asynchronous event.Currently handling them in design depends on the availability of always-on slow clocks.In this paper we present a generic asynchronous click here design scheme that doesn't require a clock and ensure a reliable functionality without associated deadlock scenariossensitive to exact arrival times of asynchronous events.

This is here enabled by a novel pulse width insensitive design method, which also requires unconventional verification methodology that ensures thorough and comprehensive pre-silicon design quality.These have been applied on the latest, ultra-low cost embedded micro-controller design targeted for cost sensitiveapplications.